Chap 1. Introduction to benchmarking Logic libraries
I have been involved in ASIC support and benchmarking Digital designs for the last 8-10 years. The dilemma of bench marking is that the vendors always try to pick the design which is best suited to meet their requirements whereas an unbiased end customer, who is looking for a fair evaluation, is trying to prove that the product he is buying will meet his end.
Evaluation is comprised of various types which may include
1. Evaluate the name of the vendor in the industry
2. Evaluate the product and determine the fair price
3. Evaluate the product by the face value or by the marketing collateral.
Looking at all this I decided to pursue a Neutral path for the evaluation of Standard cells and memory which is the main product line of Virage Logic where I am currently employed.
Here is what is needed to go this route.
1. Download a fairly comprehensive Digital Design from the opencores.org site that can meet the needs of most of the customers.
2. After downloading the first step is to make sure that the Verilog RTL and the vectors that are given with the design are correctly setup.
3. Setup Virage Std. Cell and Memory compilers for the TSMC 0.18um and also provide hooks for the other vendors as well.
4. Replace all the existing memories with the Virage memories and keep the hooks for the other vendor libraries.
5. Simulate the design using the simulation vectors provided with the design to make sure the memories are inserted correctly
6. Setup Synopsys design compiler and perform the synthesis of the design with Virage Logic library.
7. Setup Place and Route(P&R) tools and then perform the P&R.
8. During this whole exercise the documentation should be very comprehensive and all the hooks should be correctly provided in the simulation, Synthesis and P&R scripts so that any body can replace them as needed.
9. Create a web site or a blog and upload the complete design with the documentation.
In the coming chapters we will cover the details of the selected design and comprehensive explanation of the scripts used during the process
Evaluation is comprised of various types which may include
1. Evaluate the name of the vendor in the industry
2. Evaluate the product and determine the fair price
3. Evaluate the product by the face value or by the marketing collateral.
Looking at all this I decided to pursue a Neutral path for the evaluation of Standard cells and memory which is the main product line of Virage Logic where I am currently employed.
Here is what is needed to go this route.
1. Download a fairly comprehensive Digital Design from the opencores.org site that can meet the needs of most of the customers.
2. After downloading the first step is to make sure that the Verilog RTL and the vectors that are given with the design are correctly setup.
3. Setup Virage Std. Cell and Memory compilers for the TSMC 0.18um and also provide hooks for the other vendors as well.
4. Replace all the existing memories with the Virage memories and keep the hooks for the other vendor libraries.
5. Simulate the design using the simulation vectors provided with the design to make sure the memories are inserted correctly
6. Setup Synopsys design compiler and perform the synthesis of the design with Virage Logic library.
7. Setup Place and Route(P&R) tools and then perform the P&R.
8. During this whole exercise the documentation should be very comprehensive and all the hooks should be correctly provided in the simulation, Synthesis and P&R scripts so that any body can replace them as needed.
9. Create a web site or a blog and upload the complete design with the documentation.
In the coming chapters we will cover the details of the selected design and comprehensive explanation of the scripts used during the process
posted by Sohail Syed | 1:12 PM
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