CPF and UPF standards from Candence and Synopsys

Controlling the Power Dissipation in the digital ASICs with the shrinking geometries is the key to success for most of the Microprocessor and Wireless companies. Whether you are INTEL or a small startup in the wireless industry, Power is the main concern.
Total power is a function of switching activity, capacitance, voltage and the type of Transistor. We can also say that
Total Power = Dynamic Power + Leakage
Where Dynamic Power = Switching Power + Short Circuit(sc) Power =CfV^2 + V(sc)I(sc) f
Leakage Power = Sub Threshold Current + Gate Induced Drain leakage{GIDL} + Gate Oxide Leakage + Diode Reverse Bias current

Dynamic Power is reduced by reducing switching in general which means techniques like DVFS(Dynamic Voltage Frequency Scalling) or Power/Clock gating or shutoff whereas leakage is reduced by the techniques like back biasing or multithreshold libraries.

CPF(Common Power Format) from cadence and UPF(Universal Power Format) from Synopsys are two different methods of attacking the above solutions. The common theme behind the two formats is to add Power Constraint to the RTL logic similar to the timing constraint(SDC) these guys have added in the late 90's and in the first decade of 21st century. Now, it is very common to put the timing constraint separate from the RTL logic in a different file. The generally accepted format of this file is called SDC(Synopsys Design Constraint) file.

You can get the CPF and UPF standards from the Cadence and Sysnopsys web sites. These are publically available standards.

Library vendors also have to increase the number of cells and the required characterized library needed to implement these new standards.

The cells that are needed in general are Retnetion Flops, Level Shifters, AlwaysOn and Power Gating cells.
Characterization Requirement
Normally, the logic libraries supplied by the vendors for TSMC 65nm LP process contain the following Chracterized libraries.

Corners	Voltage	Temperature	Comments
SSLT	1.08v	-40C	Temperature Inversion
SS	1.08v	125C	Normal SS Corner
TT	1.2v	25C	Normal TT Corner
FF	1.32v	-40C	Normal FF Corner
FFHTHV	1.32v	125C	Leakage Corner

Now suppose the library vendors introduces another voltage domain i.e 0.81V then additional standard characterized corners required will be

Corners	Voltage	Temperature	Comments
SSLT	1.08v	-40C	Temperature Inversion
SS	1.08v	125C	Normal SS Corner
SSLTLV	0.81v	-40C	Temp Inv Low V
SSLV	0.81v	125C	Low V Corner
TT	1.2v	25C	Normal TT Corner
FF	1.32v	-40C	Normal FF Corner
FFHTHV	1.32v	125C	Leakage Corner

All the cells provided by the library vendor needs to be characterized for atleast these corners except for the level shifters. Level shifter normally work between two domains therefore we need additional characterization points for them.

Corners	Voltage Range	Temperature	Comments
SSLV	0.81 to 0.81	125C	SSLV_0.81_to_0.81
	0.81 to 1.08	125C	SSLV_0.81_to_1.08
SSLTLV	0.81v to 0.81V	-40C	SSLTLV_0.81_to_0.81
	0.81v to 1.08V	-40C	SSLTLV_0.81_1.08
SS	1.08v to 0.81v	125C	SS_1.08_to_0.81
	1.08v to 1.08v	125C	SS_1.08_to_1.08
SSLT	1.08v to 0.864	-40C	SSLT_1.08_to_0.81
	1.08v to 1.08	-40C	SSLT_1.08_to_1.08
TT	1.2v to 1.2v	25C	TT_1.2_to_1.2
FF	1.32v to 1.32	-40C	FF_1.32_to_1.32