Implementing A simple 4 bit Multiplier using CPF and UPF

Here is a very simple 4 bit multiplier design in which basically we have implemented five 4 bit multiplier and based on "sopa" and "sopb" signal, one of the multiplier is selected.

Now, we can implement power saving techniques to one or more of the multipliers and see the impact of CPF/UPF during the Synthesis or P&R flow.

Changing Mult4 to run at Lower voltage




In this particular example we have divided the Multipleir first into two power domains i.e. TOP and LS(Level Shifter).


The TOP is synthesized at SS/1.08V/125C whereas we will synthesize the LS power domain at SS/0.81V/125C.


We can see from the picture that Mult4(Power Domain LS) is talking to the TOP power domain. This is only possible if we have Step down Level shifters on the Signal Opa and Opb going into Mult4 and another set of step up Level shifters on prod4 going out of the Mult4 . Since it is 4 bit multiplier therefore we need atleast


Step up Level Shifter = 8
Step Down Level Shifter = 4

Also notice that you need a separate Power Supply fo this Block(Mult4) which is 0.81V.

Changing Mult5 to Shutdown (LOW)

In this part of the design we wanted to Shutdown Mult5 based on the Signal(pse=Power Shutdown enable). This will create another Power Domain(LOW).
During the Shutdown it is required it is also required that we keep the content of the flops retained. Therefore we need the retention flops.
The Shutdown block also requires that we put the required Power gating cells to gate the power based on the signal "pse".






RTL IMPLEMENTATION of the TOP level
module mult (clk, S_opa, S_opb, S_prod, opa, opb, prod, ice, pse, pge);
input clk, ice, pse, pge;
input [2:0] S_opa, S_opb, S_prod;
input [3:0] opa, opb;
output [7:0] prod;
reg [3:0] opa_1, opa_2,opa_3, opa_4, opa_5, opb_1, opb_2, opb_3, opb_4, opb_5;
reg [7:0] prod, prod_1, prod_2, prod_3, prod_4, prod_5;

multiplier mult_1 (.clk(clk) , .opa(opa_1), .opb(opb_1), .prod(prod_1));
multiplier mult_2 (.clk(clk) , .opa(opb_2), .opb(opb_2), .prod(prod_2));
multiplier mult_3 (.clk(clk) , .opa(opa_3), .opb(opb_3), .prod(prod_3));
multiplier mult_4 (.clk(clk) , .opa(opb_4), .opb(opb_4), .prod(prod_4));
multiplier mult_5 (.clk(clk) , .opa(opa_5), .opb(opb_5), .prod(prod_5));
demux15 demux15_1 (.out1(opa_1), .out2(opa_2), .out3(opa_3), .out4(opa_4), .out5(opa_5), .in(opa), .cntrl (S_opa));
demux15 demux15_2 (.out1(opb_1), .out2(opb_2), .out3(opb_3), .out4(opb_4), .out5(opb_5), .in(opb), .cntrl (S_opb));
mux51 mux51 (.out(prod), .in1(prod_1), .in2(prod_2), .in3(prod_3), .in4(prod_4), .in5(prod_5), .cntrl (S_prod));
endmodule