Reading Process information from FABs

DEVICE CORNERS		SSS	TTT	FFF	TFS	TSF
POLY	STD - 4nm			X
POLY	STD		X		X	X
POLY	STD + 4nm	X
NFET	15%			X
NFET	7.5%				X
NFET	ISAT(STD)		X
NFET	-7.5%					X
NFET	-15%	X
PFET	15%			X
PFET	7.5%					X
PFET	ISAT(STD)		X
PFET	-7.5%				X
PFET	-15%	X

Reading the process table from FAB is simple. I learned this a few days ago from a friend. Here is the trick.

Device Corner specified in the above table are SSS, TTT, FFF, TSF, TFS. Let's take an example of first TFS device corner. In this case T means typical Poly, F means FAST NFET, and S means SLOW PFET.

Let's look at only the POLY Section of the above table.

DEVICE CORNERS		SSS	TTT	FFF	TFS	TSF
POLY	STD - 4nm			X
POLY	STD		X		X	X
POLY	STD + 4nm	X

This indicates that there are three possible Channel LENGTHs . i.e. STD and the other two are either 4nm smaller then the STD or 4nm bigger than the STD.

Now we understand that if the CHANNEL is larger then it reduces leakage whereas if it is smaller then the leakage is more but perfromance is better if channel length is smaller and worst if channel length is larger.

Therefore, for SSS process the first S refers to increased POLY LENGTH i.e STD+4nm and for TFS since the channel length is Typical therefore it has a cross in the STD section.

DEVICE CORNERS		SSS	TTT	FFF	TFS	TSF
NFET	15%			X
NFET	7.5%				X
NFET	ISAT(STD)		X
NFET	-7.5%					X
NFET	-15%	X

Similarly if we look at the NFET portion of the table it is clear that for the SSS process NFETs has 15% less ISAT(Saturation Current) compare to the Typical NFET Saturation Current. Now, the important thing to note here is that for TSF process the NFET are faster compare to the SSS process by 7.5%